Every signal, current, and thermal path in a multilayer PCB passes through vias. Yet via geometry is often selected by habit rather than calculation. The right size balances electrical capacity, thermal performance, and manufacturing yield. It is not a single hole diameter but a system of dimensions—drill hole, finished hole, pad, anti-pad, and plating thickness—that must work together in production.
The Core Dimensions That Define a Via
A via is a plated barrel surrounded by a pad and an anti-pad. The first common error is treating drill diameter and finished hole diameter as identical. If a fabricator drills 0.25 mm and plates 25 µm on each wall, the finished hole becomes about 0.20 mm. This finished diameter determines current flow and lead clearance. Below 0.30 mm, losing 50 µm to plating is a large percentage of the hole and must be designed in from the beginning.
The pad diameter must leave enough copper for a reliable annular ring, calculated as (pad diameter − drill diameter) ÷ 2. A remaining ring of 0.125 mm on outer layers is a common baseline for mechanical vias, while inner layers often require 0.15 mm or more. The anti-pad clearance in copper planes matters just as much: too small increases capacitance, while too large disrupts the return-current path. For a 0.25 mm via, a 0.60 mm anti-pad is often a practical starting point, but high-speed designs may tune it significantly. The dominant manufacturing constraint is the aspect ratio, or board thickness divided by drill diameter. A 1.6 mm board with a 0.20 mm via is 8:1. Most fabricators handle 8:1 to 10:1 reliably; above 12:1, plating voids and barrel cracks become serious risks.
HDI builds solve this by reducing the effective via length. Blind vias and buried vias extend only through one or two dielectric layers, so a 0.10 mm laser via can be used without violating aspect-ratio limits. The same 0.15 mm drill that creates a risky 10.7:1 ratio in a 1.60 mm board becomes a safer 6.7:1 in a 1.00 mm board. Therefore, via diameter cannot be separated from stackup and plating capability.
Calculating Via Size for Current, Thermal, and Signal Requirements
A via must carry the current of the trace it connects. Its copper cross-section is a hollow cylinder, not the drilled circle. For a finished hole diameter D and plating thickness t, the barrel copper area is approximately π/4 × [(D + 2t)² − D²]. A 0.25 mm finished via with 25 µm plating has about 0.022 mm² of copper area, similar to a 0.60 mm trace at 1 oz copper. That is enough for many signals but not automatically enough for power-hungry rails or thermal paths.
For current and thermal sizing, use IPC-2152 charts rather than simplified current-per-mil rules. A 0.25 mm via may handle roughly 1.4 A for a 10 °C rise in standard conditions, but the value drops in dense boards, low airflow, or IPC Class 3 designs. Power converters, LED arrays, and motor drivers usually distribute current across parallel vias or specify 0.30–0.40 mm vias with thicker copper plating. Thermal vias are sized for heat transfer more than for current, so the number of vias and total barrel wall area are more important than a single large hole.
High-speed signals change the tradeoff. A smaller via reduces pad capacitance and saves space, but a longer barrel increases inductance. Above 5 Gbps, via stubs cause reflections and insertion loss, so back-drilling or blind-via stacking becomes necessary. The physical hole diameter cannot be optimized alone; pad, anti-pad, ground stitching, and return-path placement all shape signal integrity. For example, a 5 GHz RF board may use a 0.20 mm via with a 0.40 mm pad and a 0.55 mm anti-pad, then validate the structure with a 3D electromagnetic solver. Because these factors vary with laminate and plating chemistry, a structured method is required when Determining PCB Via Size. The design goal is not the smallest hole, but the geometry that makes the via electrically transparent at the target data rate.
Manufacturing Limits and HDI Via Size Best Practices
Mechanical drilling is cost-effective down to about 0.15–0.20 mm. Smaller mechanical holes increase drill breakage and cycle time, raising cost quickly. Laser microvias are typically 0.10 mm and can go to 0.05 mm in advanced processes. The basic rule for a microvia is depth ≤ diameter. A 0.10 mm laser via should connect layers no more than about 0.10 mm apart. Sequential lamination allows each microvia to bridge only one thin dielectric layer, keeping plating and inspection reliable.
Pad and anti-pad dimensions follow the fabrication method. A 0.20 mm mechanical via often uses a 0.45 mm pad for a 0.125 mm annular ring. A 0.10 mm laser microvia may use a 0.25–0.30 mm pad, with the larger pad improving yield and the smaller pad freeing routing space. Via-in-pad designs must be filled and planarized to prevent solder wicking and trapped air, especially under fine-pitch BGAs. This adds process steps but enables the very small vias common in HDI boards.
Real-world designs mix via types by function. An automotive radar board may use 0.20 mm through vias for RF signal transitions and 0.40 mm vias for high-current power distribution. A smartphone mainboard may use 0.10 mm laser microvias from layer 1 to layer 2, buried 0.20 mm mechanical vias deeper in the stack, and larger through vias for grounding. Standardizing on a small set of via sizes early in layout reduces drill changes, improves impedance control, and increases panel utilization. Prototype designs may use conservative dimensions for fast turns, while production runs should be tightened only after confirming the fabricator’s actual capability. Since via size is coupled to stackup, copper weight, drill type, and plane clearance, it must be determined early in the design process, not after routing is complete.